View XC4020XLXLA_8591540.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ds027 (v3.1) july 5, 2000 www.xilinx.com 1 product specification 1-800-255-7778 ? 2000 xilinx, inc. all rights reserved. all xilinx trademarks, registered trademarks, patents, and disclaimers are as listed a t http://www.xilinx.com/legal.htm . all other trademarks and registered trademarks are the property of their respective owners. all specifications are subject to c hange without notice. features ? one-time programmable (otp) read-only memory designed to store configuration bitstreams of xilinx fpga devices simple interface to the fpga; requires only one user i/o pin cascadable for storing longer or multiple bitstreams programmable reset polarity (active high or active low) for compatibility with different fpga solutions xc17128e/el, xc17256e/el, xc1701 and xc1700l series support fast configuration low-power cmos floating gate process xc1700e series are available in 5v and 3.3v versions xc1700l series are available in 3.3v only available in compact plastic packages: 8-pin soic, 8-pin voic, 8-pin pdip, 20-pin soic, 20-pin plcc, 44-pin plcc or 44-pin vqfp. programming support by leading programmer manufacturers. design support using the xilinx alliance and foundation series software packages. guaranteed 20 year life data retention description the xc1700 family of configuration proms provides an easy-to-use, cost-effective method for storing large xilinx fpga configuration bitstreams. when the fpga is in master serial mode, it generates a configuration clock that drives the prom. a short access time after the rising clock edge, data appears on the prom data output pin that is connected to the fpga d in pin. the fpga generates the appropriate number of clock pulses to complete the configuration. once configured, it disables the prom. when the fpga is in slave serial mode, the prom and the fpga must both be clocked by an incoming signal. multiple devices can be concatenated by using the ceo output to drive the ce input of the following device. the clock inputs and the data outputs of all proms in this chain are interconnected. all devices are compatible and can be cascaded with other members of the family. for device programming, either the xilinx alliance or foun- dation series development system compiles the fpga design file into a standard hex format, which is then trans- ferred to most commercial prom programmers. 0 xc1700e and xc1700l series configuration proms ds027 (v3.1) july 5, 2000 08 product specification r figure 1: simplified block diagram (does not show programming circuit) eprom cell matrix address counter ce data oe output clk v cc v pp gnd ds027_01_021500 tc oe reset/ oe/ reset or ceo
xc1700e and xc1700l series configuration proms 2 www.xilinx.com ds027 (v3.1) july 5, 2000 1-800-255-7778 product specification r pin description data data output is in a high-impedance state when either ce or oe are inactive. during programming, the data pin is i/o. note that oe can be programmed to be either active high or active low. clk each rising edge on the clk input increments the internal address counter, if both ce and oe are active. reset/oe when high, this input holds the address counter reset and puts the data output in a high-impedance state. the polar- ity of this input pin is programmable as either reset/oe or oe/reset . to avoid confusion, this document describes the pin as reset/oe , although the opposite polarity is pos- sible on all devices. when reset is active, the address counter is held at "0", and puts the data output in a high-impedance state. the polarity of this input is program- mable. the default is active high reset, but the preferred option is active low reset , because it can be driven by the fpgas init pin. the polarity of this pin is controlled in the programmer inter- face. this input pin is easily inverted using the xilinx hw-130 programmer. third-party programmers have differ- ent methods to invert this pin. ce when high, this pin disables the internal address counter, puts the data output in a high-impedance state, and forces the device into low-i cc standby mode. ceo chip enable output, to be connected to the ce input of the next prom in the daisy chain. this output is low when the ce and oe inputs are both active and the internal address counter has been incremented beyond its terminal count (tc) value. in other words: when the prom has been read, ceo will follow ce as long as oe is active. when oe goes inactive, ceo stays high until the prom is reset. note that oe can be programmed to be either active high or active low. v pp programming voltage. no overshoot above the specified max voltage is permitted on this pin. for normal read oper- ation, this pin must be connected to v cc . failure to do so may lead to unpredictable, temperature-dependent opera- tion and severe problems in circuit debugging. do not leave v pp floating! v cc and gnd positive supply and ground pins. prom pinouts capacity pin name 8-pin pdip soic voic 20-pin soic 20-pin plcc 44-pin vqfp 44-pin plcc data 112402 clk 2 3 4 43 5 reset/oe (oe/reset ) 38 6 1319 ce 4 10 8 15 21 gnd 5 11 10 18, 41 24, 3 ceo 61314 21 27 v pp 71817 35 41 v cc 82020 38 44 devices configuration bits xc1704l 4,194,304 xc1702l 2,097,152 xc1701/l 1,048,576 xc17512l 524,288 xc1736e 36,288 xc1765e/el 65,536 xc17128e/el 131,072 xc17256e/el 262,144
xc1700e and xc1700l series configuration proms ds027 (v3.1) july 5, 2000 www.xilinx.com 3 product specification 1-800-255-7778 r xilinx fpgas and compatible proms device configuration bits prom xc4003e 53,984 xc17128e (1) xc4005e 95,008 xc17128e xc4006e 119,840 xc17128e xc4008e 147,552 xc17256e xc4010e 178,144 xc17256e xc4013e 247,968 xc17256e xc4020e 329,312 xc1701 xc4025e 422,176 xc1701 xc4002xl 61,100 xc17128el (1) xc4005xl 151,960 xc17256el xc4010xl 283,424 xc17512l xc4013xl/xla 393,632 xc17512l xc4020xl/xla 521,880 xc17512l xc4028xl/xla 668,184 xc1701l xc4028ex 668,184 xc1701 xc4036ex/xl/xla 832,528 xc1701l xc4036ex 832,528 xc1701 xc4044xl/xla 1,014,928 xc1701l xc4052xl/xla 1,215,368 xc1702l xc4062xl/xla 1,433,864 xc1702l xc4085xl/xla 1,924,992 xc1702l xc40110xv 2,686,136 xc1704l xc40150xv 3,373,448 xc1704l xc40200xv 4,551,056 xc1704l + xc17512l xc40250xv 5,433,888 xc1704l+ xc1702l xc5202 42,416 xc1765e xc5204 70,704 xc17128e xc5206 106,288 xc17128e xc5210 165,488 xc17256e xc5215 237,744 xc17256e xcv50 559,232 xc1701l xcv100 781,248 xc1701l xcv150 1,041,128 xc1701l xcv200 1,335,872 xc1702l xcv300 1,751,840 xc1702l xcv400 2,546,080 xc1704l xcv600 3,608,000 xc1704l xcv800 4,715,648 xc1704l + xc1701l xcv1000 6,127,776 xc1704l + xc1702l xcv50e 630,048 xc1701l xcv100e 863,840 xc1701l xcv200e 1,442,106 xc1702l xcv300e 1,875,648 xc1702l xcv400e 2,693,440 xc1704l xcv405e 3,340,400 xc1704l xcv600e 3,961,632 xc1704l xcv812e 6,519,648 2 of xc1704l xcv1000e 6,587,520 2 of xc1704l xcv1600e 8,308,992 2 of xc1704l xcv2000e 10,159,648 3 of xc1704l xcv2600e 12,922,336 4 of xc1704l xcv3200e 16,283,712 4 of xc1704l notes: 1. the suggested prom is determined by compatibility with the higher configuration frequency of the xilinx fpga cclk. designers using the default slow configuration frequency (cclk) can use the xc1765e or xc1765el for the noted fpga devices. device configuration bits prom
xc1700e and xc1700l series configuration proms 4 www.xilinx.com ds027 (v3.1) july 5, 2000 1-800-255-7778 product specification r controlling proms connecting the fpga device with the prom. the data output(s) of the of the prom(s) drives the d in input of the lead fpga device. the master fpga cclk output drives the clk input(s) of the prom(s). the ceo output of a prom drives the ce input of the next prom in a daisy chain (if any). the reset /oe input of all proms is best driven by the init output of the lead fpga device. this connection assures that the prom address counter is reset before the start of any (re)configuration, even when a reconfiguration is initiated by a v cc glitch. other methods ? such as driving reset /oe from ldc or system reset ? assume the prom internal power-on-reset is always in step with the fpga ? s internal power-on-reset. this may not be a safe assumption. the prom ce input can be driven from either the ldc or done pins. using ldc avoids potential contention on the d in pin. the ce input of the lead (or only) prom is driven by the done output of the lead fpga device, provided that done is not permanently grounded. otherwise, ldc can be used to drive ce , but must then be unconditionally high during user operation. ce can also be permanently tied low, but this keeps the data output active and causes an unnecessary supply current of 10 ma maximum. fpga master serial mode summary the i/o and logic functions of the configurable logic block (clb) and their associated interconnections are established by a configuration program. the program is loaded either automatically upon power up, or on command, depending on the state of the three fpga mode pins. in master serial mode, the fpga automatically loads the configuration pro- gram from an external memory. the xilinx proms have been designed for compatibility with the master serial mode. upon power-up or reconfiguration, an fpga enters the master serial mode whenever all three of the fpga mode-select pins are low (m0=0, m1=0, m2=0). data is read from the prom sequentially on a single data line. syn- chronization is provided by the rising edge of the temporary signal cclk, which is generated during configuration. master serial mode provides a simple configuration inter- face. only a serial data line and two control lines are required to configure an fpga. data from the prom is read sequentially, accessed via the internal address and bit counters which are incremented on every valid rising edge of cclk. if the user-programmable, dual-function d in pin on the fpga is used only for configuration, it must still be held at a defined level during normal operation. the xilinx fpga families take care of this automatically with an on-chip default pull-up resistor. programming the fpga with counters unchanged upon completion when multiple fpga-configurations for a single fpga are stored in a prom, the oe pin should be tied low. upon power-up, the internal address counters are reset and con- figuration begins with the first program stored in memory. since the oe pin is held low, the address counters are left unchanged after configuration is complete. therefore, to reprogram the fpga with another program, the done line is pulled low and configuration begins at the last value of the address counters. this method fails if a user applies reset during the fpga configuration process. the fpga aborts the configuration and then restarts a new configuration, as intended, but the prom does not reset its address counter, since it never saw a high level on its oe input. the new configuration, therefore, reads the remaining data in the prom and inter- prets it as preamble, length count etc. since the fpga is the master, it issues the necessary number of cclk pulses, up to 16 million (2 24 ) and done goes high. however, the fpga configuration will be completely wrong, with potential contentions inside the fpga and on its output pins. this method must, therefore, never be used when there is any chance of external reset during configuration. cascading configuration proms for multiple fpgas configured as a daisy-chain, or for future fpgas requiring larger configuration memories, cas- caded proms provide additional memory. after the last bit from the first prom is read, the next clock signal to the prom asserts its ceo output low and disables its data line. the second prom recognizes the low level on its ce input and enables its data output. see figure 2 . after configuration is complete, the address counters of all cascaded proms are reset if the fpga reset pin goes low, assuming the prom reset polarity option has been inverted. to reprogram the fpga with another program, the done line goes low and configuration begins where the address counters had stopped. in this case, avoid contention between data and the configured i/o use of d in .
xc1700e and xc1700l series configuration proms ds027 (v3.1) july 5, 2000 www.xilinx.com 5 product specification 1-800-255-7778 r figure 2: master serial mode. the one-time-programmable prom supports automatic loading of configuration programs. multiple devices can be cascaded to support additional fpgas. an early done inhibits the prom data output one cclk cycle before the fpga i/os become active. d in d out cclk init done prom data clk ce ce fpga (low resets the address pointer) * for mode pin connections, refer to the appropriate fpga data sheet. v cc v cc v cc optional daisy-chained fpgas with different configurations optional slave fpgas with identical configurations reset reset ds027_02_060100 cclk (output) d in d out (output) oe/reset modes* v pp cascaded serial memory data clk ceo oe/reset 3.3v 4.7k
xc1700e and xc1700l series configuration proms 6 www.xilinx.com ds027 (v3.1) july 5, 2000 1-800-255-7778 product specification r standby mode the prom enters a low-power standby mode whenever ce is asserted high. the output remains in a high impedance state regardless of the state of the oe input. programming the devices can be programmed on programmers supplied by xilinx or qualified third-party vendors. the user must ensure that the appropriate programming algorithm and the latest version of the programmer software are used. the wrong choice can permanently damage the device. table 1: truth table for xc1700 control inputs control inputs internal address outputs reset ce data ceo i cc inactive low if address < tc (1) : increment if address > tc (2) : don ? t change active high-z high low active reduced active low held reset high-z high active inactive high not changing high-z high standby active high held reset high-z high standby notes: 1. the xc1700 reset input has programmable polarity 2. tc = terminal count = highest address value. tc + 1 = address 0.
xc1700e and xc1700l series configuration proms ds027 (v3.1) july 5, 2000 www.xilinx.com 7 product specification 1-800-255-7778 r xc1701, xc1736e, xc1765e, xc17128e and xc17256e absolute maximum ratings operating conditions (5v supply) dc characteristics over operating condition symbol description conditions units v cc supply voltage relative to gnd ? 0.5 to +7.0 v v pp supply voltage relative to gnd ? 0.5 to +12.5 v v in input voltage relative to gnd ? 0.5 to v cc +0.5 v v ts voltage applied to high-z output ? 0.5 to v cc +0.5 v t stg storage temperature (ambient) ? 65 to +150 c t sol maximum soldering temperature (10s @ 1/16 in.) +260 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc (1) supply voltage relative to gnd (t a = 0 c to +70 c) commercial 4.750 5.25 v supply voltage relative to gnd (t a = ? 40 c to +85 c) industrial 4.50 5.50 v notes: 1. during normal read operation v pp must be connect to v cc. symbol description min max units v ih high-level input voltage 2 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ? 4 ma) commercial 3.86 - v v ol low-level output voltage (i ol = +4 ma) - 0.32 v v oh high-level output voltage (i oh = ? 4 ma) industrial 3.76 - v v ol low-level output voltage (i ol = +4 ma) - 0.37 v i cca supply current, active mode (at maximum frequency) - 10 ma i ccs supply current, standby mode - 50 m a i ccs supply current, standby mode (xc1701) - 100 m a i l input or output leakage current ? 10 10 m a c in input capacitance (v in = gnd, f = 1.0 mhz) - 10 pf c out output capacitance (v in = gnd, f = 1.0 mhz) - 10 pf
xc1700e and xc1700l series configuration proms 8 www.xilinx.com ds027 (v3.1) july 5, 2000 1-800-255-7778 product specification r xc1704l, xc1702l, xc1701l, xc17512l, xc1765el, xc17128el and xc17256el absolute maximum ratings operating conditions (3v supply) dc characteristics over operating condition symbol description conditions units v cc supply voltage relative to gnd ? 0.5 to +7.0 v v pp supply voltage relative to gnd ? 0.5 to +12.5 v v in input voltage relative to gnd ? 0.5 to v cc +0.5 v v ts voltage applied to high-z output ? 0.5 to v cc +0.5 v t stg storage temperature (ambient) ? 65 to +150 c t sol maximum soldering temperature (10s @ 1/16 in.) +260 c notes: 1. stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not implied. exposure to absolute maximum ratings conditions for extended periods of time may affect device reliability. symbol description min max units v cc (1) supply voltage relative to gnd (t a = 0 c to +70 c) commercial 3.0 3.6 v supply voltage relative to gnd (t a = ? 40 c to +85 c) industrial 3.0 3.6 v notes: 1. during normal read operation v pp must be connect to v cc. symbol description min max units v ih high-level input voltage 2 v cc v v il low-level input voltage 0 0.8 v v oh high-level output voltage (i oh = ? 3 ma) 2.4 - v v ol low-level output voltage (i ol = +3 ma) - 0.4 v i cca supply current, active mode (at maximum frequency) (xc1700l) - 10 ma i cca supply current, active mode (at maximum frequency) (xc1765el, xc17128el, xc17256el) -5ma i ccs supply current, standby mode (xc1701l, xc17512l, xc17256l, x1765el, xc17128el) -50 m a i ccs supply current, standby mode (xc1702l, xc1704l) - 350 m a i l input or output leakage current ? 10 10 m a c in input capacitance (v in = gnd, f = 1.0 mhz) - 10 pf c out output capacitance (v in = gnd, f = 1.0 mhz) - 10 pf
xc1700e and xc1700l series configuration proms ds027 (v3.1) july 5, 2000 www.xilinx.com 9 product specification 1-800-255-7778 r ac characteristics over operating condition symbol description xc1701, xc17128e, xc17256e xc17128el, xc17256el, xc1704l, xc1702l, xc1701l, xc17512l xc1736e, xc1765e xc1765el units min max min max min max min max t oe oe to data delay - 25 - 30 - 45 - 40 ns t ce ce to data delay - 45 - 45 - 60 - 60 ns t cac clk to data delay - 45 - 45 - 80 - 200 ns t df ce or oe to data float delay (2,3) - 50 - 50 - 50 - 50 ns t oh data hold from ce , oe , or clk (3) 0- 0 - 0-0-ns t cyc clock periods 67 - 67 - 100 - 400 - ns t lc clk low time (3) 20 - 25 - 50 - 100 - ns t hc clk high time (3) 20 - 25 - 50 - 100 - ns t sce ce setup time to clk (to guarantee proper counting) 20 - 25 - 25 - 40 - ns t hce ce hold time to clk (to guarantee proper counting) 0- 0 - 0-0-ns t hoe oe hold time (guarantees counters are reset) 20 - 25 - 100 - 100 - ns notes: 1. ac test load = 50 pf 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. reset/oe ce clk data t ce t oe t lc t sce t sce t hce t hoe t cac t oh t df t oh t hc ds027_03_021500 t cyc
xc1700e and xc1700l series configuration proms 10 www.xilinx.com ds027 (v3.1) july 5, 2000 1-800-255-7778 product specification r ac characteristics over operating condition when cascading symbol description min max units t cdf clk to data float delay (2,3) -50 ns t ock clk to ceo delay (3) -30 ns t oce ce to ceo delay (3) -35 ns t ooe reset/oe to ceo delay (3) -30 ns notes: 1. ac test load = 50 pf 2. float delays are measured with 5 pf ac loads. transition is measured at 200 mv from steady state active levels. 3. guaranteed by design, not tested. 4. all ac parameters are measured with v il = 0.0v and v ih = 3.0v. reset/oe clk data ce t ooe ceo first bit last bit t oce t ock t cdf ds027_04_021500 t oce
xc1700e and xc1700l series configuration proms ds027 (v3.1) july 5, 2000 www.xilinx.com 11 product specification 1-800-255-7778 r ordering information valid ordering combinations xc1736epd8c xc1765epd8c xc17128epd8c xc17256epd8c xc1701pd8c xc1702lvq44c xc1736eso8c xc1765eso8c xc17128evo8c xc17256evo8c xc1701pc20c xc1702lpc44c xc1736evo8c xc1765evo8c xc17128epc20c xc17256epc20c xc1701so20c xc1704lvq44c xc1736epc20c xc1765epc20c xc17128epd8i xc17256epd8i xc1701pd8i xc1704lpc44c xc1736epd8i xc1765epd8i xc17128evo8i xc17256evo8i xc1701pc20i xc1702lvq44i xc1736eso8i xc1765eso8i xc17128epc20i xc17256epc20i xc1701so20i xc1702lpc44i xc1736evo8i xc1765evo8i xc1704lvq44i xc1736epc20i xc1765epc20i xc1704lpc44i xc1765elpd8c xc17128elpd8c xc17256elpd8c xc1701lpd8c xc17512lpd8c xc1765elso8c xc17128elvo8c xc17256elvo8c xc1701lpc20c xc17512lpc20c xc1765elvo8c xc17128elpc20c xc17256elpc20c xc1701lso20c xc17512lso20c xc1765elpc20c xc17128elpd8i xc17256elpd8i xc1701lpd8i xc17512lpd8i xc1765elpd8i xc17128elvo8i xc17256elvo8i xc1701lpc20i xc17512lpc20i xc1765elso8i xc17128elpc20i xc17256elpc20i xc1701lso20i xc17512lso20i xc1765elvo8i xc1765elpc20i xc1701l pc20 c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = ? 40 to +85 c) package type pd8 = 8-pin plastic dip so8 = 8-pin plastic small-outline package vo8 = 8-pin plastic small-outline thin package so20 = 20-pin plastic small-outline package pc20 = 20-pin plastic leaded chip carrier vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic chip carrier device number xc1736e xc1765e xc1765el xc17128e xc17128el xc17256e xc17256el xc17512l xc1701 xc1701l xc1704l xc1702l
xc1700e and xc1700l series configuration proms 12 www.xilinx.com ds027 (v3.1) july 5, 2000 1-800-255-7778 product specification r marking information due to the small size of the commercial serial prom packages, the complete ordering part number cannot be marked on the package. the xc prefix is deleted and the package code is simplified. device marking is as follows: revision history the following table shows the revision history for this document. notes: 1. when marking the device number on the el parts, an x is used in place of an el. 2. for xc1700e/el only. 3. for xc1700l only. 1701l j c operating range/processing c = commercial (t a = 0 to +70 c) i = industrial (t a = ? 40 to +85 c) package type p = 8-pin plastic dip s (2) = 8-pin plastic small-outline package v = 8-pin plastic small-outline thin package s (3) = 20-pin plastic small-outline package j = 20-pin plastic leaded chip carrier vq44 = 44-pin plastic quad flat package pc44 = 44-pin plastic chip carrier device number 1736e 1765e 1765x (1) 17128e 17128x (1) 17256e 17256x (1) 1704l 1702l 1701 1701l 17512l date version revision 7/14/98 1.1 major revisions to include the xc1704l, xc1702l, and the xq1701l devices, packages and operating conditions. also revised the timing specifications on page 9 . 9/8/98 2.0 revised the marking information for the vq44. updated "dc characteristics over operating condition" on page 7 and page 8 . added references to the xc4000xla and xc4000xv families in "xilinx fpgas and compatible proms" on page 3 and figure 2 on page 5 . 12/18/98 2.1 added virtex fpgas to "xilinx fpgas and compatible proms" on page 3 . added the pc44 package for the xc1702l and xc1704l products. 1/27/99 2.2 changed military i ccs . 7/8/99 2.3 changed i ccs standby on xc1702/xc1704 from 50 m a to 300 m a. 3/30/00 3.0 combined data sheets xc1700e and xc1700l. added ds027, removed military specs. added virtex-e and em references. 07/05/00 3.1 added 4.7k resistor to figure 2 , updated format.

▲Up To Search▲

Price & Availability of XC4020XLXLA

	To Download XC4020XLXLA Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .